`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/17 09:56:56
// Design Name: 
// Module Name: C_M_2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module C_M_2(
input [3:0]a,
input [3:0]b,
input e,
output [3:0]y,
output co
    );
    wire [4:0]ci;
    wire [3:0]bx;
    assign bx = b^{4{e}}; 
    assign ci[0] = e;
    assign co = ci[4];
    assign y = a^bx^ci[3:0]&(a^bx);
    assign ci[4:1] = a&bx|ci[3:0]&(a^bx);
    assign co = ci[4];

endmodule
